Typically, modern semiconductor memories (whether embodied in a memory integrated circuit or incorporated in a larger design, e.g., as cache memory of a processor integrate circuit) employ differential bit lines and some sort of differential amplifier or sensing circuit in their design. Such differential amplifier and sensing circuits are commonly known as sense amplifiers (sense amps) and a wide variety of sense amp designs are known in the art, including current sensing and voltage sensing variations.
Generally, when designing memory sense amps, great care is taken to balance the sense amps to reduce any offset voltage. Such balancing usually involves careful layout of the devices to ensure that matched devices are oriented identically and vary identically with mask layer misalignment, in order to achieve nearly identical device characteristics, such as mobility, threshold voltage, and overlap capacitances when fabricated. Certainly other attention is customarily directed to careful layout of the source/drain regions and interconnections in order to achieve nearly identical nodal capacitances and inter-conductor capacitances, which also help reduce sense amplifier offsets.
Unfortunately, even if devices are well matched as fabricated, one or more devices may experience a shift in one or more parameters over a long period of time. In certain very-small device technologies, data-dependent effects have begun to present themselves. One such effect is Negative Bias Temperature Instability (NBTI). Accordingly, new techniques are desired to address NBTI and other similar or related effects.